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Update Enable Circuitry
Figure 7-7: DQS Logic Block in Stratix V Devices
DQS Delay Chain
SV51008
2014.01.10
DQS Enable
00
dqsbusout
DQS/CQ or
CQn Pin
dqsin
D Q
01
10
11
The dqsenable
signal can also
come from the
FPGA fabric
PRE
dqsenable
<use_alternate_input_for
first_stage_delay_control>
7
dqsin
7
phasectrlin[1..0]
0
1
7
7
0
1
7
0
1
<dqs_ctrl_latches_enable>
DQS Postamble Circuit
offsetctrlin [6..0] 7
Phase offset
dqsenableout settings from the
1
0
D Q
D
Q
7
dqsupdateen
Update
Enable
Postamble
Enable
D Q
dqsenablein
0
1
D Q
0
1
D Q
0
1
DQS phase-shift
circuitry
DQS delay
settings from the
DQS phase-shift
<dqs_offsetctrl_enable>
7
delayctrlin [6..0]
Input Reference
Clock
Circuitry
D Q
circuitry
zerophaseclk
Postamble clock
leveling clk
This clock can come from a PLL
output clock or an input clock pin
<bypass_output_register>
Read-leveled
postamble clock
Update Enable Circuitry
The update enable circuitry enables the registers to allow enough time for the DQS delay settings to travel
from the DQS phase-shift circuitry or core logic to all the DQS logic blocks before the next change.
Both the DQS delay settings and the phase-offset settings pass through a register before going into the DQS
delay chains. The registers are controlled by the update enable circuitry to allow enough time for any changes
in the DQS delay setting bits to arrive at all the delay elements, which allows them to be adjusted at the same
time.
The circuitry uses the input reference clock or a user clock from the core to generate the update enable
output. The UniPHY intellectual property (IP) uses this circuit by default.
Figure 7-8: DQS Update Enable Waveform
This figure shows an example waveform of the update enable circuitry output.
DLL Counter Update
(Every 8 cycles)
System Clock
DQS Delay Settings
Updated every 8 cycles
7 bit
DLL Counter Update
(Every 8 cycles)
Update Enable
Circuitry Output
DQS Delay Chain
DQS delay chains consist of a set of variable delay elements to allow the input DQS/CQ and CQn signals to
be shifted by the amount specified by the DQS phase-shift circuitry or the logic array.
Altera Corporation
External Memory Interfaces in Stratix V Devices
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